library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
-----------------------------------------------
entity Top_Level is
Port ( ps2_clk  : inout std_logic;
         ps2_data : inout std_logic;
 
         clk      : in std_logic;
           rst      : in std_logic;
 
         tx_data  : in std_logic_vector(7 downto 0);
         write    : in std_logic;
 
         rx_data  : out std_logic_vector(7 downto 0);
         read     : out std_logic;
         busy     : out std_logic;
         err      : out std_logic;
         Segout   : out std_logic_vector(6 downto 0);
         Anodes   : out std_logic_vector(3 downto 0) );
 
 
end Top_Level;
-----------------------------------------------
 
-------------------------------------------------
architecture Behavioral of Top_Level is
--------------------------------------------------
 
 
component ps2interface
 
port( ps2_clk  : inout std_logic;
        ps2_data : inout std_logic;
 
        clk      : in std_logic;
        rst      : in std_logic;
 
        tx_data  : in std_logic_vector(7 downto 0);
        write    : in std_logic;
 
        rx_data  : out std_logic_vector(7 downto 0);
        read     : out std_logic;
        busy     : out std_logic;
        err      : out std_logic
        );
 
end component;
 
-----------------------------Signals-------------------------------------------
 
signal scancode : std_logic_vector (7 downto 0);
 
-------------------------------------------------------------------------------
 
begin
 
ps2interface_i : ps2interface
            Port Map ( clk => clk,
                              rst => rst,
                              ps2_clk => ps2_clk,
                              tx_data => tx_data,
                              ps2_data => ps2_data,
                              rx_data => scancode,
                              write => write,
                              read => read,
                              busy => busy,
                              err => err );
 
process(scancode(7 downto 0))
begin
  case scancode(7 downto 0) is
     when  "10001010"  => Segout <= "1111110";
    when  x"1D"  => Segout <= "0110000";
    when  x"16"  => Segout <= "1101101";
    when  x"29"  => Segout <= "1111001";
    when  x"65"  => Segout <= "0110011";
    when  x"66"  => Segout <= "1011011";
    when  x"31"  => Segout <= "1011111";
    when  x"32"  => Segout <= "1110000";
    when  x"33"  => Segout <= "1111111";
    when  x"34"  => Segout <= "1111011";
    when  x"35"  => Segout <= "1110111";
    when  x"36"  => Segout <= "0011111";
    when  x"7F"  => Segout <= "0001101";
    when  x"6A"  => Segout <= "0111101";
    when  x"3B"  => Segout <= "1001111";
    when  x"41"  => Segout <= "1000111";
 
    when others => Segout <= (others => '-');
    end case;
 
Anodes <= "1110";
end process;
 
 
end Behavioral;
 
Here is the top level we are currently trying to get to work for the keyboard interface. We cant quite figure it out, perhaps the timing is off or the in/outs are wrong, something to investigate.